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verilog复习

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嘛，testbench

`timescale 1 ns / 100 ps

每 #1 等待 1ns，精度是 100ps

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outfile = $fopen("sim_output.txt","w");
verfile = $fopen("verified.txt","r");
always @(posedge clk)
begin
if(out_valid) begin
  $fwrite(outfile,"%d\n", result_out);
  $fscanf(verfile,"%d\n", correct); 
  if(result_out !== correct)
    $display("Output error at %0d ns:
              got %0d, expected %0d”,
              $time, result_out, correct);
end
end

使用 verifile

数字代表

000…000:zero
111…111: minus one
100…000: −2n−1 (maximum negative)
011…111: 2n−1−1 (maximum positive)

Two’s complement

第一个是 1 就是负数，负数换二进制需要先二进制然后取反加一

换成正数就加一，获得十进制之后加上负号

full adder

a, b, cin, to sum, cout

cout = (a & b) & ((a xor b)&cin)

sum = (a xor b) xor cin

转换！看qmp应该绝对考的

fractional 是多少就乘以2的多少次方，化整，

convert 2.384 to 8 bits with 6 fractional bits:

  1. 2.384 × 26 = 152.576
  2. Round to 153
  3. Convert to 1001 1001
  4. Result is 10.011001 = 2.390625 (=153/64)
  5. Error is 0.006625 (absolute), or 0.28% (relative)

负数！

convert –6.73 to 10 bits with 5 fractional bits:

  1. –6.73 × 25 = –215.36
  2. Round to –215
  3. Convert to 1100101001
  4. Result is 11001.01001 = –6.71875 (=–215/32)
  5. Error is 0.01125 (absolute), or 0.17% (relative

计算到二进制

十进制小数的二进制表示：

整数部分：除以2，取出余数，商继续除以2，直到得到0为止，将取出的余数逆序

小数部分：乘以2，然后取出整数部分，将剩下的小数部分继续乘以2，然后再取整数部分，一直取到小数部分为零为止。如果永远不为零，则按要求保留足够位数的小数，最后一位做0舍1入。将取出的整数顺序排列。

如果是负数只影响整数部分，小数照常

不对，小数是正常然后整数减去小数

-5.75 整数是 -6 小数是 0.25

(−1)sign × 1.sig × 2exp−127

signed 代表使用2补表达

GPIO general purpose I/O

Pulse-width modulation (PWM) sending analog

Universal asynchronous rx/tx (UART)

multi bits sending, not check bits using 1 wire

processor

Application Specific Integrated Circuits (ASICs)

需要有什么？

A set of different arithmetic operations

不同运算方法
▶︎ Movement of data into and out of the arithmetic logic

传输结果
▶︎ A way of breaking down complex functions into simple steps

分解复杂 func 到简单步骤
▶︎ A way to “program” the circuit to carry out these steps

所以由什么组成呢？

There are a number of state-holding (clocked) elements:
▶︎Program counter register
▶︎Register file
▶︎Instruction memory

pc计数，文件？命令记录

TIMING!

我觉得应该有计算在这里

Assuming sum only output: n stage adder:
▶︎4 + 2(n – 2) gate delays

minimum clock period, T, is given by: tcQ + tp + ts < T

ts setup time, input 改变钟还没有变

th hold time, 保持一会儿不变

T > 0.6+12+0.4ns

tcq，钟信号传导到产生 out 的东西的时候，clock-to-Q delay

Fmax = 1/13ns = 76.9MHz